The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.
10 Gigabit Ethernet, a popular and growing technology, is standardized in the IEEE 802.3ae Standard. For example, the IEEE 802.ae Standard specifies a 10 Gigabit Media Independent Interface (XGMII) between a media access control layer (MAC) and a physical layer (PHY). XGMII provides a full duplex channel operating at 10 gigabits per second (Gb/s). For each direction, XGMII includes 36 parallel signals: a 32-bit data path and 4 control signals (one control signal per 8-bits of data). The total width of XGMII is 74 signals. Because of the width of XGMII, chip-to-chip, board-to-board, and chip-to-optical module interfacing using XGMII is impractical.
The 10 Gigabit Ethernet Task Force developed another interface, the 10 Gigabit Attachment Unit Interface (XAUI), that interfaces with XGMII and provides four self-clocked serial differential lanes in each direction. XAUI also operates at 10 Gb/s but requires only 16 signals, as compared to the 74 signals of XGMII. XAUI significantly reduces the number of signals and allows easier chip-to-chip, board-to-board, and chip-to-optical module interfacing as compared to XGMII.